1. Filed of the Invention
The present invention relates to a delay circuit built in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit and applied for example to a timing generating circuit.
2. Related Background Art
A conventional delay circuit employed in a timing generating circuit or the like is a circuit as shown in FIG. 12. The delay circuit is so arranged that there are a plurality of (four in FIG. 12) stages of inverter circuits, each of which is composed of a p-channel MOS (hereinafter referred to as PMOS) transistor (p 22 to p 25 in FIG. 12) and an n-channel MOS (hereinafter referred to as NMOS) transistor (n 22 to n 25 in FIG. 12) connected in complementary symmetry connection between a power-supply voltage Vcc and the ground GND. A delay time is defined as a time difference between times for which input voltage Vin and output voltage Vo reach a certain voltage (for example a half of Vcc), respectively.
FIGS. 13a, 13b and 13c show simulation results (waveforms of Vin.multidot.Va.multidot.Vb.multidot.Vc.multidot.Vo in the drawings) using the delay circuit shown in FIG. 12. FIG. 13a shows a simulation result for a case where the ambient temperature Ta is a low temperature (LT) and a characteristic of the MOS transistors (i.e., Vth) is a min value (minimum value) on the process specification. FIG. 13b shows a simulation result for a case where the ambient temperature Ta is a room temperature (RT) and a characteristic of the MOS transistors (i.e., Vth) is the typical value (standard value) on the process specification. Similarly, FIG. 13c shows a simulation result for a case where the ambient temperature Ta is a high temperature (HT) and a characteristic of the MOS transistors (Vth) is the max value (maximum value) on the process specification.
As shown in FIGS. 13a-13c, the delay time of this circuit is a summation of delay times of respective inverter circuits and is determined by the geometry of each MOS transistor and the number of inverter circuit stages.
In the conventional delay circuit as described above, however, each inverter circuit greatly changes its delay time when the characteristic of MOS transistors (i.e., Vth) or the ambient temperature changes, which results in largely changing the total delay time of the delay circuit.
Even if the circuit could be optimized by adjusting the geometry of each MOS transistor and the number of inverter circuit stages, the delay circuit still had a problem that it was impossible to keep a difference between the max value and the min value of delay time within about a double, as shown in FIG. 13a and FIG. 13c.